There are various known techniques for reducing the crosstalk that occurs between adjacent signal lines. In one technique, a signal line, i.e., a signal line used in a diagnostic operation mode, is arranged between bus signal lines, and the logic level of this signal line is fixed at a low or high level in a normal operation mode in which the bus signal lines are used. In another technique, a clock signal line is arranged between either a GND line or a VDD line (a power supply line) and a scan signal line. In still another technique, a clock signal line is arranged between power supply lines. See, for example, the following literatures.
Japanese Laid-open Patent Publication No. 2004-119921
Japanese Laid-open Patent Publication No. 2001-24172
Japanese Laid-open Patent Publication No. 2000-236066
In a semiconductor integrated circuit, crosstalk could occur between signal lines used for signal transmission in a system mode (a normal operation mode). Crosstalk could also occur between test, signal lines used for signal transmission in a scan mode (a diagnostic operation mode, a test mode, or the like). Such crosstalk that occurs in the system mode or the scan mode could cause a signal delay, a variation thereof, a timing error, or an incorrect operation. Consequently, the performance and the quality of the semiconductor integrated circuit could be deteriorated.